A ROM is an array of ROM cells. A top view of a conventional array of ROM cells is shown in FIG. 1 and a cross section of an individual cell is shown in FIG. 2. A ROM array has some cells which are conductive and some cells which are not conductive. A ROM mask process allows selective implantation of the ROM code, so that some cells are conductive and some are not. The purpose of a mask ROM process is to enable some cells to be conductive and others to not be conductive. This is accomplished by selective implantation of ions, such as boron, in the channels of the cells.
Referring to FIGS. 1 and 2, the ROM array 10 is formed on a substrate 11 having a first dopant type. Illustratively, the substrate is P-type silicon with a doping concentration of 1.times.10.sup.14 /cm.sup.3 .about.8.times.10.sup.15 /cm.sup.3. A plurality of parallel N.sup.+ type buried bit lines 12 are formed in the substrate 11. A plurality of polysilicon word lines 14 are formed orthogonal to the bit lines on the surface of the substrate 11. The ROM comprises a plurality of cells. One such cell 13 is delineated in FIG. 1 and shown in a cross-sectional view taken along line AA' in FIG. 2.
As shown in FIG. 2, the cell 13 comprises two parallel buried bit lines 12 which form source and drain regions for the cell. A channel 20 of length S is formed between the two bit lines in the cell 13. A gate oxide layer 21 is formed on top of the substrate 11. The oxide layer is thick at portions 22 which are located above the bit lines 12 and thin at portion 23 located over the channel 20. The thick portions 22 are approximately 300 to 1000 .ANG. and the thin portions 23 are approximately 100 to 200 .ANG.. A polysilicon layer is deposited and patterned to form polysilicon word line 14 over the gate oxide layer 21. A photo resist layer 25 is formed and patterned on the polysilicon wordlines 14 as a mask. The channel 20 becomes conducting when a voltage is applied on the polysilicon word line 14 over the channel 20. The boron 26 is implanted in the selected cells to raise the threshold voltage (V.sub.T) of the cell, which in turn, turn off the conducting state for the "off" cell (this programs the cell). Thus, cells implanted with boron cannot be turned on when a voltage ms applied to the appropriate word line.
Each bit line has a width W. The spacing between adjacent bit lines is S. Illustratively, W is 0.6 microns and S is 0.6 microns. When the cell dimension shrinks, i.e., a smaller device size, the bit line width also shrinks and the bit line sheet resistance increases. In addition, the punch-through voltage between adjacent bit lines becomes unacceptably low. Therefore, conventional ROM structures have unavoidably high bit line resistance and low junction breakdown problems.
It is an object of the present invention to provide a mask ROM structure and process which overcome the high bit line resistance and low injunction breakdown voltage problems of conventional mask ROM structures.
Another object of the present invention, is to provide a mask ROM structure, which has much better bit line to bit line punch-through voltage. Therefore, the memory cell can be further shrunk for higher density IC applications.